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An out-of-order (OoO) processor utilizing the Tomasulo hardware algorithm for dynamic scheduling was implemented in VHDL on a Nexys 3 FPGA. The architecture supported basic MIPS ISA instructions, complete with IFQ, dispatch units, BPB, RAS, FRL, PRF, CFC, functional units, CDB, instruction and data caches, ROB, LSQ, store buffer.
This project was developed in the summer of 2011 with lab partner, Max Chin, for USC’s Digital Design Tools & Techniques (EE-645) course, taught by professor Gandhi Puvvada.
This project was implemented on a Digilent Nexys 3 Spartan-6 FPGA board. The Nexys 3 was a digital system development platform featuring:
For development, the Nexys 3 FPGA was used with Xilinx tools such as ISE, EDK, and Chipscope.